In infrared radiation image pickup elements, the pixels undergo variations in characteristics. There are two types of the variations, that is, bias level variations, found on the element-to-element basis, and variations in device sensitivity. An infrared radiation image pickup apparatus for correcting these variations has been disclosed in Patent Document 1, filed in the name of the present Assignee. A semiconductor apparatus for implementing the function of correcting the variations has also been disclosed in Patent Document 2.
In a bolometer infrared radiation sensor, as one of the thermal infrared radiation sensor, changes in the bolometer resistance are becoming delicate due to miniaturization of the sensor size. The integration and sample hold with low noise need to be implemented for detecting such minor changes in resistance. The circuit designed for this purpose is disclosed in Patent Document 3, filed in the name of the present Assignee.
FIG. 8 depicts a circuit diagram showing a readout circuit part of the image pickup apparatus disclosed in the Patent Document 3. In this image pickup apparatus, a large number of thermo-electric transducing elements 102 are formed on a semiconductor substrate. The thermo-electric transducing elements 102, used in the present image pickup apparatus, are each formed by a bolometer formed on a diaphragm, and are sensitive to incident infrared radiations. These thermo-electric transducing elements are formed one-dimensionally or two-dimensionally on the substrate, and are switched over by a large number of pixel switches 101 and a large number of horizontal switches 103, as later explained, so that the transducing elements are selected sequentially. A bias voltage 108 is applied to the thermo-electric transducing element 102 through a bias circuit 141 made up by an Nch MOS transistor 104, an operational amplifier (OP amplifier) 105, a switch 106 and a capacitor 107. Specifically, the bias circuit 141 includes the Nch MOSFET 104, having a gate connected to an output terminal of the OP amplifier 105, while also including the switch 106 and the capacitor 107, connected in parallel with each other between the source and the gate of the Nch MOS FET 104. The source of the Nch MOSFET 104 is connected to an inverting input terminal (−) of the OP amplifier 105, while the bias voltage terminal 108 is connected to the non-inverting input terminal (+) of the OP amplifier 105. The source of the Nch MOSFET 104 is connected to one end of the switch 103, also termed the horizontal switch, the other end of which is connected to the thermo-electric transducing element 102. The OP amplifier 105 is provided for compensating for voltage drop of the gate-to-source voltage Vgs of the Nch MOS FET 104.
There is also provided a bias cancellation circuit 142, made up by a bias cancellation resistor 109, a switch 110, a Pch MOSFET 111, an OP amplifier 112 and a switch 113. An offset component in the drain current of the Nch MOSFET 104, that is, the current flowing through the thermo-electric transducing element 102, is eliminated by a bias cancellation voltage 114. More specifically, the bias cancellation circuit 142 includes a bias cancellation resistor 109 and a Pch MOSFET 111. The bias cancellation resistor 109 is connected between the power supply VCC and one end of the switch 110, and the Pch MOSFET 111 has a source connected to the other end of the switch 110, while having a gate connected to the output terminal of the OP amplifier 112. The OP amplifier 112 has an inverting input terminal (−) connected to the source of the Pch MOSFET 111, while having a non-inverting terminal (+) connected to the bias cancellation voltage terminal 114. The switch 113 is connected between the source and the gate of the Pch MOSFET 111, while the drain of the Pch MOSFET 111 is connected to the drain of the Nch MOSFET 104. Similarly to the OP amplifier 105, the OP amplifier 112 is provided for compensating for voltage drop of the gate-to-source voltage Vgs of the Pch MOS FET 111.
During the off-period of the horizontal switch 103, such as during the switching of the sequential scanning, or during the off-period of the pixel switch 101, such as during switching of the vertical lines, that is, during the period of non-selection of the thermo-electric transducing element 102, no current flows through the bias circuit 141. Consequently, the mutual conductance gm of the Nch MOSFET 104 is lowered, so that the resistance component of the feedback loop of the OP amplifier 105 is increased, and hence the phase delay is increased. Thus, it is not possible to provide for phase allowance of the OP amplifier 105.
For this reason, the switch 106 is provided between the gate and the source of the Nch MOSFET 104, in order to exercise control in such a manner that, during the period of non-selection of the thermo-electric transducing element 102, the connection of the OP amplifier 105 will be in a voltage-follower configuration. When the switch 106 is turned on, the output terminal of the OP amplifier 105 is connected to the inverting terminal (−), that is, connected in a voltage-follower configuration.
The above is similarly the case with the bias cancellation circuit 142. That is, the switch 113 is provided between the gate and the source of the Pch MOSFET 111, in order to exercise control in such a manner that, during the period of non-selection of the thermo-electric transducing element 102, the connection of the OP amplifier 112 will be in a voltage-follower configuration. The reason is that, if the bias circuit 141 performs the above control, the current in the bias cancellation circuit 142 is redundant, so that it is necessary to perform control to turn off the switch 110 in synchronization with the turning off of the horizontal switch 103.
There is also performed a resetting operation of the integrating sample hold circuit 131. It is noted that, during the period of non-selection, the bias circuit 141 and the bias cancellation circuit 142 are in invalidated states. Hence, there is provided a switch 115 for isolating the integrating sample hold circuit 131 from the bias circuit 141 and the bias cancellation circuit 142, by way of performing switching control, in such a manner that the resetting operation will be carried out reliably. The switch 115 is in an off-state during the resetting period of the integrating sample hold circuit 131.
Also, there flows no bias current in case any one of the thermo-electric transducing elements 102 undergoes pixel failure such as opening caused by process defects. Thus, the mutual conductance gm of the Nch MOSFET 104 is lowered to increase the resistance component of the feedback loop of the OP amplifier 105, so that the phase delay is increased such that no phase allowance can be maintained. Hence, the bypass capacitor 107 is provided between the gate and the source of the Nch MOSFET 104 to maintain the phase allowance.
When one circuit is subjected to oscillation, the effect of parallel integration on the other circuitry may appear through, e.g., a power supply line. Thus, the configuration of the bias circuit 141 helps assure the stabilized operation.
FIG. 9 depicts a circuit diagram showing the image pickup apparatus in its entirety, inclusive of the configuration of the readout circuit of FIG. 8 and the peripheral part. In the present configuration, a large number of thermoelectric transducing elements 202 are two-dimensionally arranged in a matrix pattern on a substrate and sequentially selected as the thermo-electric transducing elements 202 are changed over by pixel switches 201 and horizontal switches 204. There are provided two types of switches, namely switches HA and HB, as horizontal switches 204. These switches HA and HB come into play by Φ HA and Φ HB signals, which are activated in two phases A and B, respectively, during each horizontal period. There are provided pixel switches 201 at the points of intersection of signal lines 203 and scanning lines 211. The pixel switches 201 are each formed by an Nch MOSFET having a source grounded, having a drain connected via thermo-electric transducing element 202 to the signal line 203 and having a gate connected to the scanning line. The signal lines 203 are each connected via horizontal switch 204 to a readout circuit 206. The readout circuit 206 has an output connected via a multiplexer switch 207 to an output buffer 209. The multiplexer switch 207 is turned on or off by a horizontal shift register 208.
The readout circuit 206 is provided every two columns of the matrix, associated with the switches HA and HB, in order to read out a signal of each thermo-electric transducing element 202. A vertical shift register 205 sequentially selects the rows of the matrix. The horizontal shift register 208 sequentially selects the multiplexer switches 207 to transmit the output of each readout circuit 206 to the output buffer 209.
FIG. 10 depicts a timing chart showing the operation of the entire image pickup elements. Referring to FIG. 10, there are the phases A and B during one horizontal cycle period. The Φ HA and Φ HB signals are ON in the integrating mode of the respective phases. During the integrating mode period, the sample hold circuit enters into a sample mode, when the S/H (sample hold) pulse is HIGH, to sample an output of the integrating circuit. When the S/H pulse is LOW, the sample hold circuit enters into a hold mode. After resetting, the integrating operation enters into an integrating mode. In FIG. 10, the sample hold circuit enters into a sample mode, at a timing close to the end of the integrating mode, to sample an output of the integrating circuit. An output of the sample hold circuit for n channels is time-divisionally output via multiplexer.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-9-284652
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2004-20325A
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-P2003-318712A